This invention relates generally to the field of low-power integrated circuit design and more particularly to a method for optimized automatic clock gating.
Semiconductor chips are composed of complex electronic circuit arrangements. With each progressive generation of semiconductor technology the on-chip power utilized radically increases. Accordingly, one concern to chip designers is the mitigation of power consumption. In order to reduce the chip power consumption, various circuit and architectural techniques have been employed. Both dynamic power and static power are of significant concern in today's technologies. Dynamic power is the power that is generated due to switching on the semiconductor chip. Static power consumption has increased with each new technology due to higher leakage currents. These leakage currents lead to a large amount of standby or static current, even though no switching is taking place.
One method for reducing dynamic power has been the reduction of the chip cycle rate since chips consume less power when operating at lower frequencies. Operating a chip at a slower speed, however, leads to a corresponding lower performance. Lower performance is not a viable option given the insatiable customer demand for higher performance, and thus greater processing power. Another method for improving chip power consumption has been the reduction of power supply voltage across the entire chip. Since the chip power is proportional to the square of the supply voltage, any reduction in power supply voltage has a radical impact on reducing the power consumption. However, as the supply voltage is reduced the performance also reduces, creating a dilemma for the chip designer. In order to save power without adversely impacting the chip performance, chips have been segmented into different portions with different power supplies depending on the performance requirement.
A further concept that has been utilized to save power is clock gating. By gating the clock, switching power is reduced. The decision to perform clock gating and what logic circuits to gate has typically been a laborious and designer-intensive job. Given this effort and the fact that the amount of on-chip logic has grown radically, obtaining a truly optimal gating arrangement has become problematic. It is highly unlikely for a designer to identify all of the circuit portions which can be clock-gated to save power and to properly implement the clock gating. Moreover, clock gating circuitry itself occupies chip area and consumes additional power. Therefore a judicious selection of circuitry to gate and proper clock gating implementation is required.
One problem with all of these approaches is the laborious nature of identifying the sections to be optimized for power and then properly inserting the needed gating circuitry and control as needed. Typical clock-gating methodologies require the circuit designer to manually identify portions of the design to be gated. Manual identification of gated sections demands a significant amount of time from the designer, driving up the cost to produce large chip designs which are optimized for low power usage. In addition, since clock gating circuitry consumes chip area and power, it is desirable to automatically optimize the area and power consumption of the gating circuitry.
Moreover, prior solutions for deriving clock gating circuitry for an integrated circuit are generally targeted to analyzing at the RTL level, which is far removed from the actual implementation of the circuit design. Moreover, the efficient analysis of candidate blocks for clock gating have not been provided, without requiring significant computational effort. Difficulty in analyzing and evaluating candidate blocks is especially prevalent in circuit designs having interrelated enable signals for sequential logic. Furthermore, during later stages of the integrated circuit design flow, existing design automation tools do not allow flexibility in removing clock gates which were inserted in earlier stages of the design flow without causing significant disruption to the logic of the circuit.